1. Field of the Invention
The present invention relates generally to a method for controlling a memory system. More specifically, the invention relates to a method for controlling a non-volatile semiconductor memory system, such as a non-volatile semiconductor memory card.
2. Related Background Art
In recent years, a flash memory card like that shown in FIG. 1 has widely used as a storage medium for a portable information apparatus, such as a digital still camera or a PDA. NAND-type flash memories have been used and sold.
As shown in FIG. 1, a flash memory card of this type has a thin plastic package 1 having a slightly recessed portion, in which a flash memory 2 having a flat electrode with 22 pins is mounted. This flash memory card is electrically connected to a host system via a dedicated connector to input and output data.
FIG. 2 shows, as an example of a flash memory, a 16-Mbit NAND-type flash memory divided into 512 physical memory blocks. Each of these blocks is a minimum unit for an erase operation. One block is divided into 16 pages. One page is a basic unit of writing and read-out. One page comprises 264 bytes. Among the 264 bytes, 256 bytes are a user data area (data division), and the remaining 8 bytes (redundant division) are used for storing an error correcting code and a management information service.
On the other hand, personal computers manage data as logical blocks shown in FIG. 3. Five hundred logical blocks (identified by logical block address (LBA)), are set in FIG. 3. One logical block corresponds to 8 continuous sectors. That is, logical block 0 means logical sectors 0 to 7.
In ordinary personal computers, data are managed every sector (512 bytes). Therefore, the memory card stores therein data of one sector of a logical block using 2 pages of a physical block as a pair to carry out data management in units of 512 bytes. FIG. 4 shows an exemplary data storing method.
Unused normal blocks of both of the data division and redundant division are set to be “FFh”. The meanings of the respective bytes will be described below. Data Area-1 stores the first half 0 to 255 bytes of the data of 512 bytes. Data Area-2 stores the second half 256 to 511 bytes of the data of 512 bytes. The User Data Area is open to store user data, so that the use thereof is entrusted to the user. A Data Status Area indicates whether data are presumed reliable. Although an “FFh” is usually set, a “00h” is set when defective data are written (e.g., when the desired threshold voltage for the memory cell cannot be achieved or another error condition is associated with the cell). A Block Status Area indicates whether a block is good or defective. Although the “FFh” is usually set, the “00h” (initial defective block) or an “F0h” (acquired defective block) is set in the case of a defective block. Furthermore, the same value is written in the Block Status Area for all data in one block. A Block Address Area-1 indicates a logical address information of a block. Furthermore, since 8 sectors forming one logical block correspond to one of 512 physical blocks, the same values for all the data are written in the same block. Similarly, in a Block Address Area-2, the same contents as the data of the Block Address Area-1 are written. An ECC Area-1 is a 3-byte ECC code of even page data (256 bytes). An ECC Area-2 is a 3-byte ECC code of odd page data (256 bytes).
FIG. 5 shows, as another example of a flash memory, a 64-Mbit NAND-type flash memory that is divided into 1024 physical memory blocks. Each of these blocks is a minimum unit of erase. One block is divided into 16 pages. One page is a basic unit of writing and read-out. One page comprises 528 bytes. Among the 528 bytes, 512 bytes are used for a user data area (data division), and the remaining 16 bytes (redundant division) are used for storing an error correcting code and a management information service. One thousand logical blocks are set in FIG. 6. One logical block corresponds to 16 continuous sectors. That is, logical block 0 includes logical sectors 0 to 15. FIG. 7 shows a method for storing data in the 64-Mbit NAND-type flash memory.
The control of such a memory card adopts an additional writing system for writing updated data in a previously erased area when data are updated and subsequently erasing an area in which the original data were stored. Therefore, a physical block, in which data corresponding to a certain logical block exist, is not fixed and is always moving in the memory. Also, as shown in FIG. 8, the redundant division of the physical block stores therein a logical block address information indicating which logical block corresponds to the data held in the physical block. The Block Address Area-1 and the Block Address Area-2 in FIGS. 4 and 7 correspond to the corresponding logical addresses.
Therefore, the memory system searches areas for storing the logical block address information of all the physical blocks to prepare a translation table between logical blocks and physical blocks on a system RAM, usually when a power supply is turned on. After the tables are prepared once, it is possible to immediately determine the physical block corresponding to the logical block by referring to the tables. The searching operation for all the blocks is carried out once when the power supply is turned on. Naturally, if the position of the corresponding physical block changes after the data are updated, the memory system updates a logical address/physical address translation table to get ready for the next access.
However, in conventional memory systems, there is a first problem in that the RAM area required for the logical address/physical address translation table is large. The contents thereof will be described in detail below.
FIG. 9 shows a logical address/physical address translation table of a conventional 16-Mbit NAND-type flash memory. As described above, the data of one logical block, i.e., the data of 8 continuous sectors, exist in any one of 512 physical blocks in the flash memory. In order to select one block from the 512 physical blocks, 9 bits are required. If the table is formed so that an offset logical block address directly indicates a physical block for convenience of a software, 2 bytes are required for one logical block, so that a RAM area of 1 KB in total is required. For example, the address of a physical block, in which the information of logical block 5 is stored, is an address offset by 5 words (10 bytes) from the top of the table.
Thus, in the conventional method, there is a problem in that the RAM area required for the logical address/physical address translation table is very large. In general, a general purpose CPU has a RAM of about 1 KB on board as an integrated RAM. Therefore, conventionally, the logical address/physical address translation table must use 1 KB, and system configuration requires more than the integrated RAM, so that an external RAM must be provided for the system. This is a great factor in an increase in costs.
FIG. 10 shows a logical address/physical address translation table of a conventional 64-Mbit NAND-type flash memory. In this case, the data of one logical block, i.e., the data of 16 continuous sectors, exist in any one of 1024 physical blocks in the flash memory. The selection of one physical block from 1024 physical blocks needs 10 bits, so that a RAM area of 2 KB in total is required. For that reason, a very large RAM area is required similar to the 16-bit NAND-type flash memory.
This problem is more serious as the capacity of the flash memory increases. For example, the number of blocks is 8192 for the 1-Gbit capacity memories, so that a RAM capacity of 16 KB is required.
If the memory capacity increases more, there is a second problem in that the logical address can not be stored in the redundant division of the physical block of the flash memory. The Block Address Area of the redundant division of a physical block of the 16-Mbit NAND-type flash memory shown in FIG. 7 stores therein a logical block address information indicating which logical block corresponds to the data held in the physical block. FIG. 11 shows the structure of the Block Address Area of the redundant division of each physical block. In FIG. 11, four bits of D4 through D7 of a number 262 byte of an even page and a number 259 byte of an odd page are “0”, “0”, “0” and “1”, and one bit of D0 of a number 263 byte of an even page and a number 260 byte of an odd page has a fixed value “1”. Therefore, the maximum value of a block address capable of being stored is 2047 expressed by BA0 through BA10. Since 4096 physical blocks exist in a 512-Mbit NAND-type flash memory, it is not possible to store the address unless the description method for the Block Address Area is changed. Since the method for controlling the redundant division is different from those for conventional flash memories, it is not possible to control a high-capacity flash memory unless the host prepares two kinds of programs. This is a problem in that there is insufficient capacity in the program storing area of the host system for the necessary programs.
The writing and erase for a flash memory will be briefly described below. The writing in a flash memory is carried out page by page. In the case of a 64-Mbit NAND-type EEPROM, one page has 528 bytes. In addition, erase is carried out in units of a block. In the case of the 64-Mbit NAND-type EEPROM, one block is formed by 16 pages. Thus, in the NAND EEPROM, the unit of writing is different from the unit of erase. Therefore, it is not possible to erase only a certain page to update data.
When a flash memory card is used for a personal computer, it is generally treated as a drive under the control of the DOS. Parts (a) and (b) of FIG. 12 show conventional DOS format parameters, wherein part (a) shows the parameters in the case of a cluster size of 4 KB and part (b) shows the parameters in the case of a cluster size of 8 KB. The term “cluster” means a basic minimum unit of file management on the DOS. Even when a small file is stored, the file occupies one cluster. When the file size is large, the file is managed as a chain of a plurality of clusters, and its management information service is stored in a FAT (file allocation table). The size of the cluster, the management method for the FAT and so forth are managed in a sector called a boot sector. When one device is managed as a plurality of drives, its information is stored in a master boot sector. In order to carry out the writing in a file, the OS issues a write command for each cluster.
Part (a) of FIG. 12 shows the case of a cluster size of 4 KB. A master boot sector is arranged in logical sector 0, and a boot sector is arranged in logical sector 16. In addition, FATs are arranged in logical sectors 17 through 22, and the copies of the FATs are arranged in logical sectors 23 through 28. Moreover, directories are arranged in logical sectors 29 through 44, and file data areas are arranged in and after logical sector 45.
Part (b) of FIG. 12 shows the case of cluster size of 8 KB. A master boot sector is arranged in logical sector 0, and a boot sector is arranged in logical sector 16. In addition, FATs are arranged in logical sectors 17 through 19, and the copies of the FATs are arranged in logical sectors 20 through 22. Moreover, directories are arranged in logical sectors 23 through 38, and file data areas are arranged in and after logical sector 39.
Referring to FIG. 13, a conventional rewrite sequence in the case of a cluster size of 4 KB will be described. Since the cluster size is 4 KB, a write command for continuous 8 sectors is issued from the OS. At this time, the writing (data update) in logical sectors 45 through 52 (cluster A) is carried out.    (1) An erased new area is searched, and logical sectors 32 through 44 are copied on the new area NAND Block C from the original block.    (2) The new data of logical sectors 45 through 47 are written in the new area NAND Block C.    (3) The original block NAND Block A is erased.    (4) The logical address/physical address translation table is updated.    (5) An erased new area is searched, and the new data of logical sectors 48 through 52 are written in the new area NAND Block D.    (6) The data of logical sectors 53 through 63 of the original block NAND Block B are copied on the new area NAND Block D.    (7) The original block NAND Block B is erased.    (8) The logical address/physical address translation table is updated.
Therefore, when 8 sectors are rewritten, as viewed from the outside, logical sectors 32 through 63, i.e., 32 sectors in total (32 pages) are written, and the NAND Block A and the NAND Block B, i.e., 2 blocks in total, are erased within the actual device.
Referring to FIG. 14, a writing sequence in cluster B will be described below. In this case, the writing (data update) in logical sectors 53 through 60 (cluster B) is carried out.    (1) An erased new area is searched, and logical sectors 48 through 52 are copied on the new area NAND Block C from the original block NAND Block B.    (2) The new data of logical sectors 53 through 60 are written in the new area NAND Block C.    (3) Logical sectors 61 through 63 are copied on the new area NAND Block C from the original block NAND Block B.    (4) The original block NAND Block B is erased.    (5) The logical address/physical address translation table is updated. Therefore, when 8 sectors are rewritten, as viewed from the outside, logical sectors 48 through 63, i.e., 16 sectors in total (16 pages), are written and the NAND Block A, i.e., one block, is erased within the actual device.
Referring to FIG. 15, a conventional rewriting sequence in the case of a cluster size of 8 KB will be described. Since the cluster size is 8 KB, a write command for 16 continuous sectors is issued from the OS. At this time, the writing (data update) in logical sectors 39 through 54 (cluster A) is carried out.    (1) An erased new area is searched, and logical sectors 32 through 38 are copied on the new area NAND Block C from the original block NAND Block A.    (2) The new data of logical sectors 39 through 47 are written in the new area NAND Block C.    (3) The original block NAND Block A is erased.    (4) The logical address/physical address translation table is updated.    (5) An erased new area is searched, and the new data of logical sectors 48 through 54 are written in the new area NAND Block D.    (6) The data of logical sectors 55 through 63 of the original block NAND Block B are copied on the new area NAND Block D.    (7) The original block NAND block B is erased.    (8) The logical address/physical address translation table is updated. Therefore, when 16 sectors are rewritten if viewed from the outside, the write operation in logical sectors 32 through 63, i.e., 32 sectors in total (32 pages), and the erase operation from the NAND Block A and the NAND Block B, i.e., 2 blocks in total, are carried out in an actual device.
Comparing the cluster of 4 KB with the cluster of 8 KB when the same 8 KB data are written, in the case of the cluster size of 4 KB, the processing is divided into two write operations, so that the write operation consists of 48 sectors in total and an erase operation for three blocks is carried out. On the other hand, comparing with the cluster size of 8 KB in the case of the cluster size of 8 KB, the processing is concentrated on one writing, so that the write operation consists of 32 sectors in total and an erase operation for two blocks is carried out.
Thus, in the conventional memory system, when viewed from the outside, the number of the write and erase operations actually executed in the device is far greater than the number of updated sectors, so that there is the second problem in that the rewriting speed viewed from the outside decreases.
The operation of the conventional memory system when executing a file erase command will be described below. In an ordinary DOS file system, when the file erase command is executed, a mark indicating that a corresponding file is invalid is put on a directory, and a memory area having been occupied by the corresponding file is identified as open on a FAT (file allocation table). Therefore, the data division of the file body remains on the flash memory without being erased. FIG. 16 shows the relationship between a management area and a data area when an erase command is executed. In FIG. 16, for example, when erase commands for File-1 and File-4 are executed, the File-1 and File-4 are open, and a del.mark is stored. At this time, the File-1 and the File-4 are not erased from the data area.
For that reason, when a subsequent write command is executed, it is first required to carry out the erase operation of the flash memory when a data division of a new file is written in the open area. Consequently, the erase operation of the flash memory must be always carried out when the file writing is carried out, so that there is a third problem in that the file writing speed deteriorates.
The ECC Area-1 shown in FIG. 4 is a 3-byte ECC code of an even page data (256 bytes). The ECC Area-2 is a 3-byte ECC code of an odd page data (256 bytes).
The ECC (error correcting code) means a code for correcting an error. The system utilizes this error correcting code to determine whether a read data has an error. When an error exists, the system can correct the error. The required error correcting capability depends on the reliability of the flash memory itself, e.g., the cell structure of the memory. Flash memories have a plurality of data storing methods. When these flash memories are used for a system, such as a digital still camera and a PDA, error correction will be considered.
For example, a first flash memory card holds binary values “0” and “1” corresponding to the different threshold values of a memory cell shown in FIG. 17. The memory card can therefore use a 1-bit error correcting code to provide ECC for one page (256 bytes). A second flash memory card holds four-valued values “00”, “01”, “10” and “11” (2 bits) corresponding to the multiple values of the threshold of a memory cell shown in FIG. 18. The memory card that stores multiple bits per cell, illustrated in FIG. 18, therefore uses a 2-bit error correcting code to provide ECC for one page (256 bytes) since there is a possibility that 2-bit data may be erroneous when one memory cell is defective. The algorithm for generating a code and detecting and correcting an error for 1-bit error correction is different from that for 2-bit error correction.
Conventional systems (e.g., digital still cameras, PDAs) have only one kind of error correcting algorithm on board. For that reason, there is a fourth problem in that it is possible to read only one of the above described first (single bit) and second (multi-bit storage per cell) memory cards. This is an obstacle to the enhancement of flexibility of flash memories on the market.